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NTE3881 Integrated Circuit NMOS, Parallel I/O Interface (PIO), 4MHz
Description: The NTE3881 Parallel I/O Circuit (PIO) is a programmable, two port device which provides a TTL compatible interface between peripheral devices and the NTE3880. The Central Processing Unit (CPU) can configure the NTE3881 to interface with a wide range of peripheral devices with no other external logic required. Typical peripheral devices that are fully compatible with the NTE3881 include most keyboard, paper tape readers and punches, printers, PROM programmers, etc. The NTE3881 utilizes N channel silicon gate depletion load technology and is packaged in a 40-Lead DIP type package. Features: D Two Independent 8-Bit Bidirectional Peripheral Interface Ports with "Handshake" Data Transfer Control D Interrupt Driven "Handshake" for Fast Response D Any One of Four Distinct Modes of Operation may be Selected for a Port, including: Byte Output Byte Input Byte Bidirectional Bus (Available on Port A Only) Bit Control Mode D All with Interrupt Controlled Handshake D Daisy Chain Priority Interrupt Logic Included to Provide for Automatic Interrupt Vectoring without External Logic D Eight Outputs are Capable of Driving Darlington Transistors D All Inputs and Outputs Fully TTL Compatible D Single 5 Volt Supply and Single Phase Clock Required Absolute Maximum Ratings: Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +70C Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to +150C Voltage On Any Pin With Respect to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6W Note 1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics: (TA = 0 to 70C, VCC = 5V 5% unless otherwise specified)
Parameter Clock Input Low Voltage Clock Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Power Supply Current Input Leakage Current Tri-State Output Leakage Current in Float Tri-State Output Leakage Current in Float Data Bus Leakage Current in Input Mode Darlington Drive Current Symbol VILC VIHC VIL VIH VOL VOH ICC IL1 ILOH ILOL ILD IOHD VIN = 0 to VCC VOUT = 2.4 to VCC VOUT = 0.4V 0 VIN VCC VOH = 1.5V Port B Only IOL = 2.0mA IOH = -250A Test Conditions Min -0.3 VCC-0.6 -0.3 2.0 - 2.4 - - - - - -1.5 Typ - - - - - - - - - - - - Max 0.80 VCC+3 0.8 VCC 0.4 - 70 10 10 -10 10 - Unit V V V V V V mA A A A A mA
Capacitance: (TA = +25C, f = 1MHz unless otherwise specified)
Parameter Clock Capacitance Input Capacitance Output Capacitance Symbol C CIN COUT Test Conditions Unmeasured Pins Input Capacitance Min - - - Typ - - - Max 10 5 10 Unit pF pF pF
AC Characteristics: (TA = 0 to 70C, VCC = 5V 5% unless otherwise specified)
Parameter Clock Cycle Time Clock Width (High) Clock Width (Low) Clock Fall Time Clock Rise Time CE, B/A, C/E, to RD, IORQ Setup Time Any Hold Time for Specified Setup Time RD, IORQ to Clock Setup Time RD, IORQ to Data Out Delay RD, IORQ to Data Out Float Delay Data In to Clock Setup Time IORQ to Data Out Delay (INTA Cycle) M1 to Clock Setup Time M1 to Clock Setup Time (M1 Cycle) Symbol TcC TcCH TcCL TfC TrC TsCS(RI) Th TsRI(C) TdRI(DO) TdRI(DOr) TsDI(C) TdIO(DOI) TsM1(Cr) TsM1(Cf) CL = 50pF Note 4 Note 3 Note 2 Test Conditions Note 1 Min 250 105 105 - - 50 0 115 - - 50 250 90 0 Typ - - - - - - - - - - - - - - Max - 2000 2000 30 30 - - - 380 110 - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 1 TcC = TwCh + TwCI + TrC + TfC. Note 2. TsCS(RI) may be reduced. However, the time subtracted from TsCS(RI) will be added to TdR(DO). Note 3. Increase TdRI(DO) by 10ns for each 50pF increase in loading up to 200pF max. Note 4. Increase TdIO(DOT) by 10ns for each 60pF increase in loading up to 200pF max.
AC Characteristics (Cont'd): (TA = 0 to 70C, VCC = 5V 5% unless otherwise specified)
Parameter M1 to IEO Delay (Interrupt Immediately Preceding M1) IEI to IORQ Setup Time (INTA Cycle) IEI to IEO Delay IEI to IEO Delay (after ED Decode) IORQ to Clock Setup Time (To Activate READY on Next Clock Cycle) Clock to Ready Delay Clock to Ready Delay STROBE Pulse Width STROBE to Clock Setup Time (To Activate READY on Next Clock Cycle) IORQ to PORT Data Stable Delay (Mode 0) PORT DATA to STROBE Setup Time (Mode 1) STROBE to PORT DATA Stable (Mode 2) STROBE to PORT DATA Float Delay (Mode 2) PORT DATA Match to INT Delay (Mode 3) STROBE to INT Delay Symbol TdM1(IEO) TsIE(IO) TdIEI(IEO) TdIE(IIOr) TsIO(C) TdC(RDYr) TdC(RDYf) TwSTB TsSTB(C) TdIO(PD) TsPD(STB) TdSTB(PD) Note 5 Note 5 CL = 50pF, Note 5 Note 5 Note 4 Test Conditions Note 5, Note 6 Note 6 CL = 50pF, Note 5 Note 5 Min - 140 - - 220 200 150 150 200 - 230 - - - - Typ - - - - - - - - - - - - - - - Max 190 - 130 160 - - - - - 180 - 210 180 490 440 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TdSTB(PDz) CL = 50pF TdPD(INT) TdSTB(INT)
Note 4 For Mode 2: tW(ST) > tS(PD) Note 5 Increase these values by 2nsec for each 10pF increase in loading up to 100pF max. Note 6. 2.5 TcC > (N-2) TdIEI (IEOG) + TdM1(IEO) + TsIE(IO) + TTL Buffer Delay, if any.
Pin Connection Diagram D2 D7 D6 Chip Enable Control Data Select Port B/A Select A7 A6 A5 A4 GND A3 A2 A1 A0 A STB B STB A RDY D0 D1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 D3 D4 D5 M1 IORQ RD B7 B6 B5 B4 B3 B2 B1 B0 (+) 5V System Clock Input IEI INT IEO B RDY
40
21
1 2.055 (52.2)
20 .550 (13.9) Max .155 (3.9)
.100 (2.54)
.019 (0.5)
.137 (3.5)
.650 (16.5)

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